1. Field of the Invention
The present invention generally relates to a method and apparatus for performing automatic tests on a printed circuit board (PCB) or card and, more particularly, to a network test circuit and method that utilizes a unique pulse and sequential count to detect and locate opens and shorts on card networks.
2. Description of the Prior Art
The IEEE (Institute of Electronics and Electrical Engineers) 1149 standard addresses the growing demand for a means of performing in-circuit testing. The standard provides several important functions: external network (net) testing, internal functional testing, and a sample mode. The external testing provides a means for testing for opens and shorts on printed circuit board (PCB) or card networks. The other two functions provide a means for testing the function of the chip itself.
The IEEE standard proposes a four pin interface which each chip should provide. The four pins are a mode pin, a scan-in pin, a scan-out pin, and a pin for the test clock. The IEEE standard also defines a boundary circuit which each chip should provide at every input/output (I/O). This boundary circuit is where the testing takes place.
The operation of a boundary scan is fairly straight forward. In a system, the scan-out and scan-in pins for the chips are connected so that the boundary scan latches in those chips form a ring. The test patterns for the chips are then scanned into the output boundary latches. The pattern of "1s" and "0s" is held at these output latches while the input boundary latches receive the result. The resulting pattern is then scanned out of the input boundary latches and compared to the expected result. If the expected pattern differs from the received pattern, a problem exists. All tests and result gathering are conducted at the test speed provided by the test clock.
In practice, the boundary scan technique is much more complicated than described above, and considerable research has been and continues to be devoted to test pattern generation, fault isolation, and fault detection. However, the foregoing description should provide a basic understanding of how the boundary scan technique works.
The IEEE 1149 standard led to a flurry of activity in boundary scan techniques. One area of particular concentration is pattern generation; i.e., what is a good set of test patterns to scan into the boundary registers? At the 1988 International Test Conference, Abu Hassan et al. presented a paper entitled "Testing and Diagnosis of Interconnects Using Boundary Scan Architecture" which describes a walking sequence test pattern. The walking sequence consists of a pattern, for example a logic "1", which is scanned through the boundary latches. In the case of the walking "1" pattern, a logic "1" is shifted into the first output boundary register, the test is begun, and the input boundary registers latch in the result. The resulting pattern is shifted out and the number of logic "1s" is counted. If the number of logic "1s" received is too few or too many, a faulty net exists. The walking sequence test pattern may be used to detect OR-shorts, stuck-on-one (S-A-1) faults, AND-shorts, and stuck-on-zero (S-A-0) faults. The walking sequence has the advantages that it is easy to use and very time efficient.
Matthias Gruetzner, in "Design for Testability for Wafer-Scale Integration Interconnect Systems Design and Test Methodology", Proceedings of the 1988 International Test Conference, 1988, pp. 146-152, describes an echoregister circuit. This circuit receives the results from a boundary test, then "echoes" them back to the sender. In this procedure, the device under test needs only to be accessed at one end.
Also relevant to the art of testing electrical circuit boards using boundary scan techniques are the following references:
R. W. Bassett et al., "Boundary-Scan Design Principles for Efficient LSSD ASIC Testing", IBM Journal of Research and Development, vol. 34, no. 2/3, March/May 1990, pp. 339-354.
Dirk van de Lagemaat and Harry Blecker, "Testing a Board with Boundary Scan", Proceedings of the 1987 International Test Conference, pp. 724-730.
Colin Maunder and Frans Beenker, "Boundary-Scan: A Framework for Structural Design-for-Test", Proceedings of the 1987 International Test Conference, pp. 714-723.
Paul T. Wagner, "Interconnect Testing with Boundary Scan", Proceedings of the 1987 International Test Conference, pp. 52-57.
In the patented literature, U.S. Pat. No. 4,991,174 to Mori et al. discloses a fault diagnostic distributed processing method and system. Mori et al. are primarily concerned with fault detection and isolation in distributed systems and, therefore, is not directly applicable to the problem solved by the subject invention. One major difference is the matter of time-out. In the Mori et al. patent, the tester has to wait a period of time (i.e., it has to time-out) before it realizes that there is a problem. This approach is not suitable to efficient printed circuit board testing.
The location of opens and shorts on a PCB or card is a difficult task when a bed-of-nails test cannot be easily performed. The need for such a testing mechanism arises, first, during laboratory debugging and, second, during field test. The testing for opens and shorts is needed during laboratory debugging when the card manufacturing process has not been completely established and is still unreliable. It is also needed during debugging when engineering changes are made. These changes have the potential of adversely affecting the card networks (e.g., solder bridges may be accidently made or networks accidently cut). In the field, when a card defect is suspected of causing a system malfunction, a means for testing for opens and shorts without a bed-of-nails tester is also required.
The echoregister circuit of Gruetzner allows testing where pins would normally be inaccessible. However, the echoregister does not return responses sequentially so that multi-drop nets cannot be tested. The walking sequence proposed by Hassan et al. provides the sequential response lacking with the echoregister circuit, but this approach does not allow the testing of multiple pins at system speed; rather, the test is performed at service clock speed. In addition, while both approaches provide a good level of confidence in the test results, better fault isolation than either can provide is desired.